Towards an Automated Design of Application-specific Reconfigurable Logic

Reconfigurable architectures can bridge the gap between programmable solutions (processors, DSPs) and highly optimised ASICs if they are structured in an application-specific way. Two of the main disadvantages of reconfigurable logic are its low functional density, caused by the area overhead introduced by configuration logic and memory, but also reduced clock frequencies, caused by extended signal paths and sub-optimal placement and routing possibilities. In particular, fine-grained generic structures like FPGAs suffer from this deficiency and some coarse-grained architectures were developed to correct this situation. Coarse-grained reconfigurable architectures expose a high performance but they are designed more specific to their application domain in terms of the hardware functions they directly provide inside their cells. A second way to increase functional density in reconfigurable architectures is to apply run-time reconfiguration to reuse the resources in time. In [1], Wirthlin et al. define a functional density measure. Based on this measure, it can be shown that the functional density of reconfigurable architectures can be increased by run-time reconfiguration. Onthe-fly changes of structural properties of a circuit must be directly supported by architectural features of the hardware and dynamic reconfiguration is therefore an intensively investigated area. Our previous work [2] has shown, that area and energy efficiency can only be achieved by highly adapted circuits which can be characterised as applicationspecific reconfigurable architectures, a result which is supported also by related work [3]. Dynamic reconfiguration is an inherent feature of such circuits. The main challenges for application-specific reconfigurable architectures are their design and the organisation of the reconfiguration sequencing. Associated with this are open issues on how to integrate them into an embedded system environment, or, more specific, into a real-time processing system. Currently, application-specific reconfigurable structures must be designed manually for each situation, resulting in high NRE costs and a complete lack of programming tools. An integration must also be done manually and no general programming model is supplied. The objective of our current work is to develop the methodologies and supporting algorithms to advance an automated design of the reconfigurable fabric itself and its integration into a processor environment and tool flow. The integration strategy we want to support is the systematic extension of a processor’s instruction set architecture (ISA). Looking at the micro-architecture, the fabric